The observation and assumptions

For the purpose of discussion, we will make the following assumptions -

- In mid-late 2006, Intel occupies ~80% market share with three 300mm 65nm fabs, while AMD occupies ~20% with only 90nm FAB30 (200mm) and FAB36 (300mm).
- AMD's FAB30 has the same wafer throughput as Intel's 65nm fabs. FAB36, while under 90-to-65nm transition and having low utilization, further increases production volume by 50%.
- Intel's main production in 3Q 2006 is Core 2 Duo and dual-core Netburst, with Core 2 Quad volume small enough to be negligible to our discussion (e.g., 10% or less).
- The most significant factor except those described above are the yield of the fabs, and AMD's FSB36 has about the same dual-core K8 yield as its 90nm counterparts.

The calculations

Potentially, three 300mm 65nm fabs would have 3*2*2 = 12x capacity of one 200mm 90nm fab, if the yields of all fabs are the same. Thus, counting into AMD's FAB36, Intel would've had 12x/1.5 = 8x capacity of AMD with the same (dual-core processor) yield. However, Intel's market share during the period is only 4x that of AMD's. There is thus a 2x discrepancy between Intel's potential capacity (8x of AMD's) and its true capacity (4x of AMD's), which is presumably affected by a lower yield of its fabs. In other words, to reach the expected market share, AMD's FAB30 and FAB36 would have yields twice as good as Intel's 65nm 300mm fabs.

Apparently, this conclusion is not possible. A factor of two in terms of yield is too large, and Intel simply can't be that bad in manufacturing. A few factors may have affected the estimation accuracy here:

- Intel's 65nm fabs may have lower wafer throughput or utilization than AMD's FAB30 and FAB36 combined, particularly the Ireland fab which was ramping for just 4 months, and D1D which is also used for 45nm research & development.
- Intel may be making much more Core 2 Quad, which effectively cuts production volume in half (two Core 2 Duo dies make one Core 2 Quad).

The Implication

So how does this 1.5x yield difference affect "native" quad-core manufacturing? Suppose AMD's dual-core K8 yield is 81%; Intel's Core 2 Duo yield would be just 54% (1/1.5x). By 1st-order estimate, AMD's native quad-core would have a yield of roughly 65% (0.81*0.81), whereas Intel's would have 29% (0.54*0.54). In other words, out of 100 quad-core dies, AMD is able to make 65 functional quad-core processors, while Intel only 29, less than 50% of its smaller competitor. It is not difficult to see why AMD is going native but Intel won't until late 2008.

Lets for the purpose of discussion turn the parameters further in Intel's favor, and assume it has just 1.25x lower yield (instead of 1.5x) from AMD's. If we again suppose dual-core K8 has yield 81%, then Core 2 Duo would have almost 65%, making Intel's MCM quad-core approach as productive as AMD's native quad-core approach. What we see here is that a yield just a quarter better than the competitor could've made a huge difference in terms of native quad-core manufacturability. In fact, Not only is Intel late to native quad-cores, it was also late to native dual-cores for about 6 months even with a better technology (65nm vs. 90nm).

The conclusion is clear, that Intel is telling the truth that it can't make native quad-core cost-effectively. For AMD, it might be very hard, but probably still doable, based on a simple capacity observation and this back-of-envelope calculation.

The arguments

Some people have argued the precision of the above estimates. Their arguments can basically be divided into the following points:

- Intel's D1D is also making 45nm transition in late 2006, thus should have less than maximum output.
- Intel's Ireland fab, ramping only 4 months from Jun'06, won't achieve max capacity in Oct'06.
- Intel's shipping more dual-core processors in 4Q06 than AMD. Specifically, just over 50% of Intel processors are dual-cores, while only 30% of AMD's are.
- AMD's FAB36, making 300mm wafers and started revenue shipping in Apr'06, should've been making as much silicon as FAB30.
- By late 3Q06, AMD would also have Chartered's output at hand.
- Intel's 65nm doesn't actually result in 2x capacity of 90nm, more like 1.7x (1/0.6). As well, Intel's 300mm wafer would result in ~2.25x usable silicon area of 200mm ones.

The first point, it turns out, is wrong. As D1D's making 45nm outputs, its 65nm capacity is moved to the neighboring D1C, which is outputting 65nm chips right after Ireland and purposely/completely ignored by me above. The second point would be valid and reduce 65nm Ireland fab's capacity to some 30% of its max.

The third point above is also true; however it fails to recognize that most of Intel's single-core processors (Celerons and Pentium M's) are made at its 90nm fabs, whereas all of AMD's single-core and dual-core processors are made out of FAB30 & 36 (excluding Chartered), a factor the 17% difference in dual-core ratio isn't even able to compensate.

The fifth and sixth points are minor. Chartered's flex capacity would account for up to 20% of AMD's silicon output, and even less in Oct'06, not 3 months after its first revenue shipping for AMD. Assume Chartered is supplying 15% of AMD's silicon output, it'll effectively make output from AMD's own fabs 85% of the total, or changing the actual Intel-to-AMD output ratio from 4x to 4.7x.

The forth point, which we'll discuss last here, seems quite valid from page 5 of this AMD Jun'06 analyst day presentation (see picture above). At late 3Q06, the 300mm "wafer outs" from FAB36 seems to be 0.4x of the max 200mm from FAB30, equivalent to 0.4*2.25 = 0.9x FAB30's silicon area. Surely this is a great increase of AMD's potential capacity. Unfortunately, it turns out such argument is unfounded and mislead by a graph without y-axis unit and meant to be illustrative only.

If we read the text on page 4 of that presentation (again see picture above), FAB36 is expected to output 25k wafers per month (wpm) by Q4 2007, which will be the total 300mm wafer output at that point (FAB38 won't have wafer outs until Q1 2008). We also know FAB30 is outputting about 30k wpm in Q3 2006. Now go to page 5 again and look! How can green line's 25k wpm (end of 4Q07) be some 60% higher than red line's 30k wpm in 2006? It is absolutely not possible unless the "wafer outs" y-axis actually means wafer area outs, and the 25k 300mm wpm from FAB36 is effectively doubled to 50k, some 66% higher than the 30k 200mm wpm from FAB30.

It turns out my original estimate of FAB36 reaching 50% capacity of FAB30 is actually a bit optimistic. The true number should be calculated as such: (0.8/3.4 * 25000)*2.25/30000 = 0.44, where 0.8 comes from green line at end of 3Q06, 3.4 from end of 4Q07 (both FAB36 only), 25000 is expected green line wpm at end of 4Q07, 2.25 translates 300mm wpm to effective 200mm wpm, and the final 30000 is FAB30 wpm (red line at end of 3Q06).

Overall, a definitely more precise/probably more accurate estimate is the following:

Intel's potential capacity: (2+0.3)*(1/0.6)*2.25 = 8.6

AMD's potential capacity: 1+0.44 = 1.44

Potential capacity ratio: 8.6/1.44 = 6.0x

Intel's actual output: less than 80% market share (excluding 90nm production)

AMD's actual output: 20%*0.85 = 17% (Chartered effects)

Actual output ratio: 80%/17% = 4.7x

Discrepancy between potential and actual output: 6.1/4.7 = 1.28, or almost 28% difference in microprocessor yield, well between the 50% and 25% estimates I made above.

## 29 comments:

I didn't notice you included any Inel chipset production in your calculations.

AbinsteinI will admit I am suprised that I do not see where you have accounted for dual core mix for both AMD and Intel.

Looking at the Q4 2006 earnings calls, Intel was above 50% for dual cores, while AMD was at about 33%.

So if Intel makes 80 chips, 40 are dual core.

If AMD makes 20 chips, 7 are dual core.

That would seem to play a role in your differences, and as such your numbers would need to be revised to reflect this.

Also you claim that the die size for Netbust is larger than for Core 2 Duo, which does not match what Anandtech has for die sizes, 143mm^2 for Core 2 Duo, and 162mm^2 for Netburst Pentium D 900.

The conclusion is clear...You like logic and facts, well those are two facts that were over looked.

------------------------------------

PS: Thanks for the explanation of an AMD platform (HTT and DC) on Sharikou's Blog.

"I didn't notice you included any Inel chipset production in your calculations."I have the impression that Intel's chipsets are manufactured on a technology node one generation lower than its processors. After all, Intel does not sell all its 90nm fabs once the transition to 65nm is made. I could be wrong, though. But read the assumptions - without inside information, I cannot claim to be accurate, but only guess on the most significant factors.

"Looking at the Q4 2006 earnings calls, Intel was above 50% for dual cores, while AMD was at about 33%."The difference is easily offset by a better yield of Netburst-based dual-core processors (see below also). Note that Core 2 Duo would most likely occupy less than 66% of Intel's 50% dual-core processors. In any rate, a 8x potential manufacturing capacity with 4x actual shipping unit is not right. Unless you can prove that Intel's

dual-coreunit share is much different/higher than itsoverallunit share, the above numbers you quoted have little significance to my estimates."... what Anandtech has for die sizes, 143mm^2 for Core 2 Duo, and 162mm^2 for Netburst Pentium D 900."TwoNetburst dies combined is slightly larger thanoneCore 2 Duo. The net effect is thus dual-core Netburst has much better yield, which is determined by per-die size, than Core 2 Duo.No offense but your calculations are terrible because they are based on flawed assumptions. A few errors:

1) You fail to account for actual wafer starts and assume all fabs have same production capacity (and choose to only account for node size and wafer size). You mention throughput - I'm not sure by this if you mean wafer processing time in the fab (that is generally what it would mean). Failing to account for actual fab size and wafer throughput are both considerable errors.

2) As other have pointed out you assume similar single/dual/quad mix for AMD and Intel

You then adjust arbitrarily for both 1 and 2 by ~50%

3) You assume Intel's fabs are 100% CPU production. This is mostly, but not quite completely, true.

4) Your 65mn production for Intel is wrong - Intel claimed crossover (meaning just more than 50%) in Q3'06 (may have been late Q2?) - it is unreasonable to think that they would have gone from crossover to 100% 65nm in less than 6 months.

5) You ignore Apple production (albeit it is small) as Apple is not counted in the market share #'s that are generally reported.

6) You exclude Itanium which is probably fine as these are done on a older tech. Not sure if these are done in the main CPU fabs either.

7) You ignore relative aggregate die size differences.

8) You assume 65nm is 2X 90nm, while on paper it is, in reality it is not - look no further than AMD's 90nm vs 65nm AthlonX2's...

While you can say "back of the envelop" to justify your attempt to prove some preconceived notions on yield - the assumptions are too flawed to do the calculations you are doing. While you mention early on your point is not to comment on the validity of your calculations - you can't do the rest of the article with these errors and expect to get a believable result.

I can make a bunch of incorrect assumptions to plug into calculations to prove that Intel has 25% better yield than AMD, of course that would be no more true than what you did here.

"Two Netburst dies combined is slightly larger than one Core 2 Duo. The net effect is thus dual-core Netburst has much better yield, which is determined by per-die size, than Core 2 Duo."

Your yield understanding is driven by an assumption that yield is driven to random defects. This is not the case in the real world. I'm not trying to single you out specifically - I see a lot of people in many blogs assume yield is driven purely by random defects.

Worst case is X^2, unless of course there is an inherent issue in the design, however the yield of something twice the area is not X^2 where X is the yield of the smaller die (if you have 2 random defect on one quad core die, it still only kills one die). The smaller the die the greater the probability of having only 1 defect on a given die, whereas greater die size increases the chance of having multiple defects. To put it more mundanely if you have 40 random defects per wafer you will not have the same probability of losing 40 dual and 40 quad core. In your theoretical case this would make less of a yield drop off between Native and MCM.

Yields are also generally driven by edge die performance (thus NOT COMPLETELY RANDOM), the center die generally yield extremely well with a fallout with increasing radius and that is due to process effects on the edge of the wafer that can stack up as well as some specific edge related issues - adhesion, bevel/scribe defects, edge rolloff on some processes like CMP...

If you start modeling yield as a percentage of wafer radius, a bigger die size will have a much steeper drop off in terms of total yield than smaller die.

Also from an economics perspective you are ignoring bin splits and this will also hit "native" designs much worse as the speed bin of the part is limited to the slowest of the 4 cores (where as with MCM you are limited by the slowest of two cores and can then pair it with an equally clocked part). The same goes for power if you have power variation across the wafers (which happens to some extent due to leakage variation caused by process variation from center to edge)

"If you start modeling yield as a percentage of wafer radius, a bigger die size will have a much steeper drop off in terms of total yield than smaller die."You've spoken of some properties about yield (whether true or false, relevant or not), then said my estimation is wrong. However I fail to see the connection between what you said and what I estimated. Please note that a steeper drop of native yield would affect AMD and Intel alike, thus inherently changes nothing of my conclusion, that native is hard for AMD but a "can't" for Intel.

Also, it is indeed that defect is not completely random, and die performance is affected mostly by edge-to-center die difference. The first point actually works in favor of native quad-cores, because if defects tend to concentrate, then two defects on a small area can kill two dual-cores (thus one full MCM'd quad-core) but only one native quad-core; it is the purely randomized defects that are most harmful to large dies. The second point may affect output binning results, making less percentage native quad-cores reaching the same high clock rate. We clearly see this from AMD's expected Barcelona release roadmap.

"No offense but your calculations are terrible because they are based on flawed assumptions. A few errors:"It occurs to me that you did not read my assumptions. I do not claim to consider all factors, only the most significant ones. You admit in multiple items that the issue is

mostlyas I assumed, or the otherwise effect issmall. Thus fundamentally your list do not go to my consideration in the first place. I'm publishing your comments only because you made some effort to make up these higher-order effects.Also, "wafer throughput" should be easy enough to understand. In short, it is the number of wafer output per unit time (e.g., a week). If you have evidence that AMD's FAB30/FAB36 has much higher wafer throughput than Intel's 65nm fabs, then contribute and let us know; otherwise your speculation is no better than mine.

Let's look at margins. Intel has 50% with seemingly over capacity and AMD's is in the gutter. Who can afford to make such a huge die now?

With 2 dies, Intel has more room to select chips that bin at high clocks, more likely than a quad with all 4 at full speed. Less engineering resources. Better yields. Hazzah.

enumae-The math in one of your comment was wrong, and was thus not published. Firstly, you offer no explanation as to where the 40/7 and 40/13 come from. Secondly, with 5.7x in dual-core and 3.0x in single-core, the overall difference would be a weighted average of the two (thus falls between 3.0 and 5.7), certainly

not8.7x.Abinstein100 chips, Intel 80, AMD 20

Intel

50% of 80 is 40, meaning 40 dual cores and 40 single cores.

AMD

33% of 20 is 7, meaning 7 dual cores and 13 single cores.

40 / 7 = 5.7x the amount of dual cores.

40 / 13 = 3.0x the amount of single cores.

-------------------------------

Why would it be a weighted average?

"Why would it be a weighted average?"Lets say you have 5.7x $20 bills of mine, and 3.0x $10 bills of mine. Do you have 8.7x the total money of mine? Nop. The actual amount of money you have vs. mine would be an weighted average of 5.7x and 3.0x, weights depending on how much percentages I own in each type of bills.

In your example above, the actual capacity ratio would've been calculated as follow:

(40*2+40)/(7*2+13) = 4.44x, where each dual-core is counted doubly w.r.t. each single-core. Note this calculation is very optimistic toward Intel, because most of the dual-core chips sold in 3Q06 are Netburst based (MCM'd) with much better yields than Core 2 Duo. This number is still far from the 8x potential production capacity advantage from Intel.

On the yield size (which I have a background in) - your assumptions are good for random defect modes (for example a random particle) however this is generally not the greatest source of yield loss.

Most folks' yield understanding (not trying to single you out specifically) is that a bad die is due to a single defect in a large area which is otherwise "good". However on the edge you have yield issues due to process variation...it is not always about a specific singular defect on the die but systemic variation which eventually leads to a failure.

As the variation becomes large enough within a given die you have a greater chance of die loss. A good design obviously takes some WID (within die) variation into account but the larger the die size the larger the WID, especially at the edge of the wafer and the greater the chance of die loss. This is not a linear (by die area) effect.

Taking another stab at this - if you can withstand variation "X" (say metal loss after CMP, remaining etch stop layer thickness after initial etch, poly Si overetch, critical CD variation, etc...), the probability of falling outside of that allowable variation increase exponentially, not linearly, with die size.

On a side note this effect also leads to more binsplit issues with larger die (once again more than just linear by area)

So when it comes to edge yield you cannot assume a defect density and then calculate good die. It is not a matter of 10 defects on edge die equating to 10 bad quad core or 10 bad dual core (5 MCM). It is probability of area A falling withing a certain process window, vs area B falling in that process window.

Hope this helps your readers a bit...

"Potentially, three 300mm 65nm fabs would have 3*2*2 = 12x capacity of one 200mm 90nm fab, if the yields of all fabs are the same. Thus, counting into AMD's FAB36, Intel would've had 12x/1.5 = 8x capacity of AMD with the same (dual-core processor) yield."

Are you assuming F36 is only 1/4 ramped? If you assume it is 1/2 ramped than it is roughly the equivalent of F30 when you account for 200mm vs 300mm....

Thus your calculation should be 12/2 not 12/1.5....

So now you have 6X capacity when the market says 4X capacity. Now if you correct for Intel's greater dual core mix, less than perfect 2X scaling for 65nm, the numbers are suddenly close to a wash and your theoretical yield differences are now non-existent.

For example if you assume 65nm dies size is 60% of 90nm die (instead of 50%, which die size data that is available as well as SRAM cell size sclaing suggests), you now get:

Intel = 3 (fabs) x 2 (wafers size) x 1.66 (90nm vs 65nm)

= 8.4 (equiv 200mm, 90nm fab)

AMD = 1 (200mm fab) + 0.5 x 2 (300mm half ramped X wafer size correction)

= 2 (equiv 200mm, 90nm)

Now the ratio is 4.2!

Now correct for dual core mix and some of the second order effects...

Please let me know if I made a mistake anywhere.

"However on the edge you have yield issues due to process variation...it is not always about a specific singular defect on the die but systemic variation which eventually leads to a failure.

As the variation becomes large enough within a given die you have a greater chance of die loss. A good design obviously takes some WID (within die) variation into account but the larger the die size the larger the WID, especially at the edge of the wafer and the greater the chance of die loss. This is not a linear (by die area) effect.

...

So when it comes to edge yield you cannot assume a defect density and then calculate good die. It is not a matter of 10 defects on edge die equating to 10 bad quad core or 10 bad dual core (5 MCM). It is probability of area A falling withing a certain process window, vs area B falling in that process window.

Hope this helps your readers a bit..."

Thanks. This is one of the most helpful and informative comments I get on this blog. I just had to include most parts of it in this reply. ;-)

Some anonymous-"Intel - 80% market share, let's say ~60% of which is dual core (Intel stated >50% dual core production)"You are tweaking in an unrealistic way. Intel's claim of over 50% is more like 51% than 60% to me. You also seem to imply the same yield from MCM'd Netburst dual-core and native Core 2 dual-core. With these inaccuracies, you have no position to talk about any higher-order effects.

Some other anonymous-"Are you assuming F36 is only 1/4 ramped?"Yes, I am assuming the wafer output of FAB36 is about a quarter to that of FAB30. Note that the number cannot be as high as 50% as you suggested, because at that time AMD was ramping at full speed to 65nm, which is scheduled to end-of 4Q06 launch and 1Q07 crossover. Part of FAB36 is even used to make initial revision of Barcelona.

"For example if you assume 65nm dies size is 60% of 90nm die (instead of 50%, which die size data that is available as well as SRAM cell size sclaing suggests), you now get:"A 60% instead of 50% shrink would've made Intel's 65nm potential capacity 6.67x instead of 8.0x. It is still much larger than the actual number (4.5x at the low-end).

"Yes, I am assuming the wafer output of FAB36 is about a quarter to that of FAB30. Note that the number cannot be as high as 50% as you suggested, because at that time AMD was ramping at full speed to 65nm"

And this is based on?

I hate to resort to using actual facts on this blog but look at Page 5 straight from the horse's mouth:

http://www.amd.com/us-en/assets/content_type/DownloadableAssets/DarylOstranderAMDAnalystDay.pdf

300mm wafers OUT in Q4 is roughly 1/2 200mm wafer outs, this would put die out at roughly the same level. Q3'06 was not much different in fact, which would indicate to me the impact of starting to ramp 65nm was felt as a leveling off of the F36 capacity temporarily, not as a decrease / underutilization! Either way you can speculate - I'll look at AMD's own #'s...

This would be consistent with smart manufacturing planning and use of factory swing space - unique 65nm tooling (~30% of equipment is new for each node, the remainder of the equipment can be reused) was added before the unique 90nm tooling was taken down so as not to impact the overall capacity. AMD also touts APM3.0 for efficient use of manufacturing capacity and the fact that AMD uses shared transistor technologies between the end of 90nm and beginning of 65nm gen (CTI) should also vastly reduce / eliminate the "underutilization" impact (which I think is born out in AMD's analyst day foils)

So, if AMD's analyst day foil is believed to be true, this would make your AMD portion of your ratio as 2 not 1.5 like you theorize. Factor in 65nm scaling and your discrepancy is gone...

You can continue to quibble with each of the specific impacts (actual 90nm-65nm scaling benefit), but when you start to add these things up your discrepancy theory starts to evaporate.

For example you assume in Q4 Intel was at 3 full 65nm fabs - this clearly is not the case as the link you provided showed Ireland's first 65nm outs were in Jun'06 (Hence why Otellini was in there in the first place) - there is no way Intel could have gone to 100% ramp in 3-6 months. In all honestly, though this was probably made up by some for the 90nm Intel fabs which you ignored (while largely chipset capacity, Intel was still producing 90nm CPU's in Q4'07)

"You also seem to imply the same yield from MCM'd Netburst dual-core and native Core 2 dual-core. With these inaccuracies, you have no position to talk about any higher-order effects."

My calculation were based on how much Si and raw capacity would be needed based on relative market shares (much like you did). You can add yield in later but if you look at the numbers carefully everything was normalized back to single core, 90nm equivalent. For dual core I assumed the Si needed was twice that of a single core - I'm not implying same yield.

Likewise I assumed no differences in yield between AMD's single and dual core products...

The analysis was based on how much relative Si raw capacity would be need to provide the relative market share amounts. If you have some actual yield data on single vs dual core products, I'd be happy to add it in.

If we are going to start factoring in yield - you will now need to to factor in 200mm vs 300mm yield, 90nm vs 65nm yield, in addition to the dies size yield impacts.

I'm curious to get your thoughts on those analyst foils though...

enumae-Your latest comment was published. I don't know how better could I acknowledge receiving your feedback?

Some anonymous-"300mm wafers OUT in Q4 is roughly 1/2 200mm wafer outs, this would put die out at roughly the same level. Q3'06 was not much different in fact,"If you want to believe the accuracy of that graph (which has no y-axis unit and is obviously for illustration purpose), then firstly, in the graph there's a bump on 300mm 3Q06 output but a dip on 200mm; while the latter is around 0.75 grid, the latter about 1.8 grid, making total output (1.8+2.25*0.75)/2 = 1.74x that of a single 200mm fab max level. Secondly, note that the 300mm wafer throughput in the graph might include 65nm testing/ramping wafers, which we did not take into account; if we do, the ratio would be even lower.

"AMD also touts APM3.0 for efficient use of manufacturing capacity"I don't think you understand APM, which is mainly used to track wafer performance vs. parameters, but this is off topic.

"AMD uses shared transistor technologies between the end of 90nm and beginning of 65nm gen (CTI) should also vastly reduce / eliminate the "underutilization" impact"A 25% fab utilization at the same time of heavy 90-to-65nm retooling (Q3, not Q4)

isgood utilization."this would make your AMD portion of your ratio as 2 not 1.5 like you theorize. Factor in 65nm scaling and your discrepancy is gone..."Your math is so crude that it completely negates your demand on high precision. As explained above, a more precise estimate of (FAB30+FAB36)/FAB30 ratio would be ~1.7,

assuming the same level of wafer throughput in FAB30 and Intel's 65nm fabs. The last assumption is quite arbitrary, and could render any higher-order estimate that you've insisted on meaningless.To consider the imperfect (60%) 65nm scaling, we'd also the better-than-double (225% according to Intel) scaling from 200mm to 300mm. Thus Intel's potential capacity should be 3*(1/0.6)*2.25/1.7 or about 6.6x that of AMD's, which is still much higher than the actual number of 4.5x (taken into account different dual-core percentages). The discrepancy is 1.46x, still much worse than the 1.25x used in my optimistic estimate. In the end, even with higher precision,

nothing is gone."For example you assume in Q4 Intel was at 3 full 65nm fabs - this clearly is not the case as the link you provided showed Ireland's first 65nm outs were in Jun'06"I assumed a lot of things, such as any of Intel's 65nm fab has the same wafer throughput as AMD's FAB30. Now, if you know for a fact it is not the case, or if you know exactly how much percentage the Ireland fab have ramped in 6 months (starting from Mar'06), please contribute. Otherwise you are not making any constructive argument.

"Now, if you know for a fact it is not the case, or if you know exactly how much percentage the Ireland fab have ramped in 6 months (starting from Mar'06), please contribute."

So in absence of data again we'll assume your RIDICULOUS assumption of 100% is accurate and leave a number which is obviously wrong until there is actual data, which conveniently enough is about as publicly available as yield data.

And it's not 6 months / Mar'06; we're talking wafer outs (not starts here). Why must you try to cook the books at every turn? First wafer outs WERE IN JUNE. If we want Q3 OUTS (assuming Q3 = Jul-Sep?) this is less than 3 months. You're confusing starts with outs...

Thus to find out AVERAGE Q3 output you need (roughly) average Q2 wafer starts. I say rough because wafer cycle time is generally 3-4 months. This would be 3 months after the ramp starting in Mar'06 (actually less as you are averaging Apr-Jun, but what the hey, I'll throw you a bone). On a side note the reason the first lots cam out in 3 months (or potentially slughtly less) is that obviously with not much running in the fab at that point these become priority lots and can be pushed with faster cycle times. As the fab starts to become more loaded the cycle tiems tend to decrease a bit (my 3-4 months is an estimate, but obviously 3 months is the lower bound /best possible case which is what we want here as the desire is to make Ireland's capcity as large as we can in order to help the ratio #'s...)

A rational person however would not just assume 100% in the absence of data and then refuse to change it even knowing it's wrong... but let's look at a normal fab ramp time and then divide by the time in question.

1 year is a ridiculous fast ramp time and that would be a good upper bound (READ: MAX) for output. so 1 quarter into a 1 year ramp would put the fab at about 25% capacity. (In reality the ramp is probably closer to 1.5-2 years but I don't have specific data as you requested. Intel may also have front loaded some of the ramp - although generally speaking it is fairly linear)

So am I contributing now? Do you not think 0.25 is a more reasonable than 1.0 as an estimate for Ireland's fab 65nm output?

"So in absence of data again we'll assume your RIDICULOUS assumption of 100% is accurate"I've never said my numbers are accurate. I don't care how you believe it or not; just don't put words that I've never said under my name. What I did say, however, is that

your crude math & unrealistic claims add nil to the precision nor accuracy."And it's not 6 months / Mar'06; we're talking wafer outs (not starts here)."By the end of 3Q06 (Sept-Oct), Intel's Ireland fab would've been running for more than 6 months, with increasing wafer output for almost 4 months. While it's not to reach the fab's maximum capacity, a 50% would've been optimistic and 30% would've been conservative. Note that AMD expects to

fullyconvert FAB30 from 200mm to 300mm in ~3 quarters, from 1Q08 to 4Q08,whilepumping out working chips at the same time. Do you believe Intel with much more money will ramp a brand new fab much slower?No matter how stubborn you are to accumulate all factors in Intel's favor, as I said your stubbornness are mostly irrelevant and contribute no accuracy to the estimate. Do you know for a fact that Intel's Ireland fab has the same max throughput as AMD's FAB30? I stated up front that I don't; the value could be anywhere from 20k to 60k wafers per month, with FAB30 roughly 30k around that time. For all reasons I believe Intel's fabs are going to be on the higher range rather than lower.

"1 year is a ridiculous fast ramp time and that would be a good upper bound (READ: MAX) for output."Ramping is a function of investment and execution. 1 year would be a good ramping execution for AMD, but won't be as good for the rich giant Intel.

"Do you not think 0.25 is a more reasonable than 1.0 as an estimate for Ireland's fab 65nm output?"Unfortunately, you are not. Your main problem is to mistaken precision for accuracy. If your goal is to estimate the Ireland ramping percentage in Oct'06, then yes, 25% would be a better number than 100% (though I believe the real number lies between 30% to 50%). However, the question here is how much more potential capacity Intel's 3 fabs have against AMD's 2, where one of the 3 (Ireland) and one of the 2 (FAB36) are both ramping at that time. Without information such as max wafer throughput from each fab, there's no more accuracy with higher precision in the numbers, and even lower accuracy when you try to make the precision toward your purposed favor.

Some anonymous-I'm sorry not to publish your (long) comment because 1) it's badly organized, 2) you didn't understand what I said and brought the discussion off-track too much. As a courtesy, however, I will still respond to it here.

"This "dip" in the graph (on a graph by the way which you claim is only for "illustartive purposes") is not the point... "No, the dip is everything

if you believe the accuracy of the graph(some people just tend to ignore this phrase). The dip shows that, as FAB36 is ramped up faster, AMD expects FAB30 production to be adversely affected. Your claim that FAB36 has wafer throughput 0.4x of FAB30 could only be true when FAB30 experience the dip at that time.In any rate, the estimate of (1.8+0.75*2.25)/2 = 1.74x would be the most accurate value,

if the graph's apparent geometric accuracy is to be believed. In fact, however, AMD's FAB36 onlyjuststarted revenue shipping around Aug06. Now there goes your 50% (or 100%?) additional potential capacity from AMD, and it's probably back to my previous 1.5x (or even less) rather than 1.74x. All in all, my estimate was purposely not made overly precise without more accurate information, and I've already estimated quite conservatively in favor of Intel."If you look at Q3 and Q4, my point is 300mm wafer outs are just a bit less than 2.25X the 200mm wafer outs, which would mean the 300mm fab is roughly the equivalent of another 200mm fab."If you really look at the role of FAB36 and its production, you should know that it's used mainly for 2 purposes: 1) test-run 300mm wafers, 2) ramping up 65nm productions. Volume production of 90nm chips at FAB36 is never AMD's main focus, though it surely not hurts. This alone should debunk your claim that FAB36 is making as many 90nm chips as FAB30.

"I have brought:- Actual effective 200mm AMD fab count based on AMD data (which you are trying to now downplay)"

I proved you wrong with the graph you linked, but obviously you couldn't understand. So be it. The readers can decide for themselves. I also show you wrong that FAB36 is by no mean producing as much 90nm silicon as FAB30 at that time, not even 50% if the link from Anandtech is to be believed. My guess if you won't (even try to) understand, either, and again, so be it.

"- A real 90nm-65nm scaling #"This is an effect as high-order as the "real" 200-to-300mm scaling. You selectively pick the former up probably because it makes your beloved Intel look better (or worse in terms of technology).

"- A more accurate count of Intel's fab (assuming there was not a miraculous 1 quarter ramp in Ireland)"The number of Intel's 65nm fabs, no matter how you count it, is 3. Effectively, the production might be only 2.3-2.5, but probably over a base capacity higher than AMD's FAB30 (~30k wpm). I'm not even counting Intel's 90nm production (which would be responsible of the large unit volume of Celerons, Pentium M's, and Smithfield-based Pentium D's). Also, now we know that FAB36 has very little capacity compared to FAB30 in Aug.06.

"Intel 2.25 fabs x 2.25 scaling x 1/0.6 (65nm scaling) = 8.44...

Ratios:

8.44 / 1.9 = 4.44

(this is counting AMD'd 300mm with 2.25X scaling)"

Your calculation is biased and wrong. The 2.25 from Intel is too low. First week of June marks the first 65nm wafer output from Ireland; till end of October, it's more than 4 months of ramping, which Intel would definitely do better than 25%. The 1.9 from AMD (FAB36 adding 90% 90nm capacity to FAB30) alone is ridiculous. There is no where that this can be true. However, for the sake of discussion, lets

stillput things in your favor, except the ridiculous ones:1. We'll assume Intel

onlyhas 2.33 65nm fabs for processor production, andnoneof its 90nm fabs is making a cent worth of microprocessors.2. We'll assume AMD's FAB36, which

juststarted 90nm revenue shipment in Aug.06 and in the process of converting for 65nm shipment in Dec.06, adds 50% capacity to FAB30 within a quarter.The ratio, which again is strongly in your/Intel's favor, is thus 2.33*(1/0.6)*2.25 / 1.5 = 5.8x of Intel's potential capacity over AMD's. When you divide that by the 4.5x actual capacity ratio estimate, you get a discrepancy roughly 1.29x.

I hope you understand now why my article claims a "back-of-envelope" calculation, and why I somewhat arbitrarily cut the 1.5x discrepancy by half (actually a rough square-root) to 1.25x in my "conservative" estimation. This is how engineers do "back-of-envelope" estimate with numbers of crude accuracy - we first go slightly toward one end, then cut back a reasonable range to the other.

AbinsteinDo you believe Intel with much more money will ramp a brand new fab much slower?This is just a thought, but did you consider that Intel may not ramp as fast as AMD because they have more than just two fabs?

enumae-What you said is possible, but IMO unlikely. Intel has much more resource than AMD, much more than 3x. The problem AMD faces today is being cache short, which directly impact its ramping speed; the problem Intel faces today is not short of resource, but to crush the cache short rival.

Some anonymous(probably multiple) -A comment not well organized and has spelling and grammar errors all over the places, plus irrational insults and tampered language has no hope to be posted here. Sorry.

However, again as a courtesy, I will rephrase some (valid or invalid) points in this response.

One anonymous:"You claim Intel can go from first revenue shipments in Jun to >33% capcity in Q3"I've always said "end of Q3" or Q3/Q4 (which means Sep/Oct), but not Q3 alone (which means Jul-Sep).

Another anonymous:"1) As of Q2'06 AMD was using Chartered 90nm capacity. (see same analyst day foils that I previously linked to for confirmation). Originally this was 3000WSPM until they dialed this back to 1000WSPM in Q1'07."According to AMD's June 1 analyst day presentation, Chartered 90nm production is just underway. If they had been shipping chips from Chartered, they'd definitely had said something like "revenue shipping." No, they couldn't say so. By the end of Oct'06, however, Chartered could've represented up to 20% of AMD's output. Note that in AMD's own terms, the "flexible capacity" Chartered offers never represents more than 20% of total silicon. There's no reason that AMD would be conservative about this.

"2) There is ABSOLUTELY no way Intel could have had an AVERAGE 33% Q3 output in Ireland when their first outs occurred in June."Read my article and comments again. I probably didn't spell it out explicitly like to a 3-year-old every time, but it should be obvious that I was talking about Q3/Q4, Sep/Oct 2006 from the beginning. Assuming a full year for Intel's Ireland fab to ramp, 4 months (June, July, August, September) should be roughly 33%. Absolutely impossible???

"3) D1d is not a full 65nm HVM fab (though you conveniently count it as one). It is in a similar situation (qualitatively, not quantitatively) as F36 , which you coneveniently de-rate to 0.25 ramp due to 65nm development and ramp."No. D1D, being Intel's largest individual clean room, together with D1C are more equivalent to FAB30+FAB36 (although likely somewhat less efficient). While D1D is ramping 45nm, its 65nm is moved to neighboring D1C. The capacity loss should be small unless the transfer is poorly executed. In fact, it's already very conservative to count D1D as one 65nm fab and ignore the 65nm capacity of D1C.

"4) Intel probably had 0.5-1.0 worth of a 90nm fab producing CPU's as you suggest in that time period."The 90nm fabs produce all Celeron, Pentium M, and Smithfield-based Pentium D during late Q3/early Q4 2006. These chips account for more than half of Intel's total processor units. (Almost all 65nm chips at that time, Yonah, Presler P-D, and Core 2 Duo, are priced higher than Intel's Q3 average selling price.)

"5) I'm assuming your dual core mix calculations are correct. Of course I originally used YOUR 200mm/300mm scaling factor and you railed on me for that when it (you) were wrong."I "railed on you" because you try to make estimate selectively more precise but consequently less accurate. If you want to make things more precise, you gotta make all of them so; if some parts you can't, then you're not adding to the accuracy at all, and likely subtracting from it.

"So, here's my final thought - I realize you assume there is no possible way that your 25% better yield calculation could possibly be wrong, but is there a possibility that yields may actually be close to even?"Here's my final thought: You didn't read my article. Please go back to read its first paragraph. I'm not asking you to agree with me, but I do believe your analysis, which calls for higher precision one-sided, is less accurate than mine.

"So I guess you can once again pick and choose what you want to argue against and for the points that you are not able to credibly challege or may have a less than favorable impact on your conclusions"Firstly, I am not obligated to even respond to some comments which apparently come from some lack of reading. Less am I to those containing flaming arguments. Further less am I to publish statements that make quotes partially or incorrectly.

Secondly, you summarize your arguments to 5 points and a final thought, which are essentially all included above.

Yet another anonymous:"As you indicate AMD is ramping their capacity over 1 year (from Q1-Q4'08)"A full year ramping would be from 4Q07 to 4Q08, not from 1Q08 to 4Q08. Lets say the first wafer out happens in the middle of Q1, and max capacity is reached in the middle of Q4. How many quarters in between? 3 or 4?

"Your calculation is based on average Q3 output (as market share #'s cover the whole quarter not just Sept)"No, from the start, my calculation has been for the end of Q3. As Intel ramps up 65nm (in Ireland), it ramps down 90nm elsewhere, probably D1C. The market share remains roughly the same, and Intel's 50+% dual-core is only reached in 4Q06. Thus a representative steady point would be late Q3/early Q4.

"I'm trying to provide a lower bound as you have provide an upper bound which has every factor in AMD's favor"You are factually wrong. My upper bound did not consider better-than-double advantage of 300mm, nor any of Intel's 90nm capacity, nor the fact that Intel's fabs are likely to have higher max throughput than AMD FAB30. Intel was making bulk Si whereas AMD SOI; at 65nm (w/o double patterning) it's definitely easier for the former to reach higher throughput than the latter.

"Here's my lower bound (Intel best case)

F22 - 1.0 65nm fab

D1d - 0.6 65nm fab

Ire - 0.3 65nm fab

Misc - 1 90nm fab (or 0.6 65nm fab)

TOTAL - 2.5 65nm fab equiv (as of Q3)

200mm, 90nm equivalent: 2.5 x 2.25 x (1 / 0.6) = 9.375"

Your D1D estimate is plain wrong. As I've linked above, 65nm production from D1D is shifted to D1C when 45nm wafers start. Losing 20% would've been very bad under such circumstance. Your 90nm estimate is also wrong. The 90nm microprocessors probably still account for 1/4 or more of Intel's total silicon (assuming 1/2 low-end units) in late 3Q06. It can't be just one single fab.

The pessimistic (in terms of potential capacity) estimate should be more like (1+0.8+0.33)*(4/3)*2.25*(1/0.6) = 10.7. The 4/3 takes into account the 90nm capacity.

"AMD (again best case in Intel's favor)

F30 - 1 (200mm, 90nm)

F36 - 0.9 (200mm, 90nm equiv)

Charterd - 0.25 (200mm,90nm equiv - based on 300WSPM of 90nm 300mm)

Total = 2.15

Ratio = 9.375/2.15 = ~4.4"

There is simply no way for FAB36 to make first revenue shipment in April, and achieves the same level of output as heavily expanded FAB30 in October. No way. According to AMD June 1 '06 analyst day presentation, FAB36 is expected to reach 25k wpm in 4Q07. Suppose it is only ramping 90nm and have no 65nm transition what-so-ever, from April to October would be less than 1/3 to max capability. Thus FAB36 would at the very best (assuming no 65nm transition) output 70% silicon of the heavily expanded FAB30.

Thus the optimistic potential capacity from AMD would be 1+0.7+0.25 = 1.95, making the potential capacity ratio, in Intel's favor, 10.65/1.95 = 5.46.

To some anonymous-I'm not going to respond to your (excessively flamming - IMO) comments one after another. Please however read the "The arguments" section added at the end of the blog article. It should cover most of the "

this is not precise" arguments.Your math is very convoluted in the arguments section regarding Chartered and there is an error...

Intel's potential capacity: (2+0.3)*(1/0.6)*2.25 = 8.6 (NO CHANGE)

AMD's potential capacity: 1+0.44 = 1.44 (NO CHANGE)

Let's just add Chartered in here as % of a fab instead of all the crazy ratios you do which is not accounting for Chartered raw capacity correctly...

Chartered's 3000 WPM (90nm, 300mm) x 2.25 is ~6700 (90nm,200mm equvalent) which is 0.225 of AMD's 30K F30 capacity (30K/6.7K).

So AMD's potential capacity is

1+0.44+0.225(chartered) = 1.665

Putting the Intel / AMD ratio at:

8.6 / 1.665 = 5.16 (not the 6.1)

5.16 / 4.7 = 1.09 or almost a 10% difference (rounding up to be nice) in microprocessor yield well within the 50% to 25% estimate you made.....ummm....

The whole point of all this is rather small changes (like counting Chartered's capacity correctly) can really swing the model - that alone took your # from 28% down to 9% without changing any other #. If you start to look harder at the potential error counting F36 as 0.2 fabs (0.44/2.25) instead of something slightly greater and that could also significantly swing the #.

These so called "high order effects" are actually not high order at all and are fairly substantial. I think I showed this with the Chartered capacity alone. (which only added 0.225 of a 200mm fab to AMD's capacity)

The key here is small changes to AMD's capacity will swing the ratio considerably, you would need more substantial changes in intel's capacity to substantially change the ratio. For every 10% of a 200mm fab you are off on estimating AMD's capacity you need to be off by nearly 1/2 a 200mm fab on Intel's side to offset it.

BTW - the wafer out discrepancy on the graph you link is not due to 200mm vs 300mm area size (thus there is also some error on how you are counting F36 capacity), if you care to seriously listen to why I think this let me know and I'll post a comment on it.

"5.16 / 4.7 = 1.09 or almost a 10% difference (rounding up to be nice) in microprocessor yield well within the 50% to 25% estimate you made.....ummm....The whole point of all this is rather small changes (like counting Chartered's capacity correctly) can really swing the model - that alone took your # from 28% down to 9% without changing any other #."

This is completely wrong and I regret that I have to deal with comments like this over and over. Firstly, you cannot include Chartered into AMD's

potentialcapacity, because you don't know whether Chartered and AMD have the same yield. AMD see no raw capacity from Chartered but the actual processor shipment.Secondly, if you assume Chartered and AMD have the same yield and include both into AMD's potential capacity calculation, then you must also include Chartered production into the actual shipment calculation. In other words, if you adjust AMD's potential capacity up from 1.44 to 1.665, then you cannot exclude Chartered 15% from its actual processor shipment. This means the discrepancy ratio in your way would be 5.16/4 (rather than 4.7) = 1.29x.

"the wafer out discrepancy on the graph you link is not due to 200mm vs 300mm area size"The "wafer outs" are normalized to number of 200mm wafers, period.

"In other words, if you adjust AMD's potential capacity up from 1.44 to 1.665, then you cannot exclude Chartered 15% from its actual processor shipment. This means the discrepancy ratio in your way would be 5.16/4 (rather than 4.7) = 1.29x.

You are absolutely right the that denominator should be 4.

However I posted a subsequent article which I think shows fairly conclusively that you can't assume the dual core mix is a wash between Intel and AMD... the delta would be 1.15 (which would effectively like putting a 4.6 where the 4.7 is) - the error is still there and acknowledged! (Thanks)

The wafer out discrepancy is not simply 200mm vs 300mm wafer size. I think it is some screwy calculation which may factor both wafer size and tech node...(although I'll concede even if true it won't change the Q3'06 #'s)

The Q4'07 point @ ~25K (F36 buildout) does not scale correctly to 45K in Q4'08 for just wafer outs (AMD stated on previous page they will add 20K over Q1-Q4'08 when F30 is fully built out on 300mm).

There also is a significant uptick in Q1'2009 which might be consistent with conversion of some capacity to 45nm....

"Firstly, you cannot include Chartered into AMD's potential capacity, because you don't know whether Chartered and AMD have the same yield."

I agree with this but you have to start somewhere. I could say the same thing about your assumption that Chartered accounts for 15% of AMD's production....if you only know Chartered's wafer starts how could you make that assumption?

What is rather ironic is our #'s are nearly the same.

If I assume Chartered is .225 and AMD's own capacity is 1.44 fabs, Chartered would represent .225/1.44 which would be 15.6%! So before you give me a hard time, realize our assumption is nearly the same regarding Chartered and it is just being stuck into the model at a different point in time.

So if my assumption on Chartered is wrong, so is yours as they are about the same :)

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